1. Technical Field
The present invention relates in general to high density electronic packaging which permits optimization of the number of circuit elements to be included in a given volume, while still allowing easy interconnect with other portions of a system. More particularly, the present invention relates to multiple laminated chip packages and to combinations of multichip packages in single systems or subsystems.
2. Description of the Prior Art
Advances in state of the art electronics technology, and in particular technology associated with integrated circuits, continue to provide steady improvement in the cost and performance of electronic circuits, particularly in the digital electronics and computer related fields. The complexity of integrated circuits has increased substantially in the years since such circuits were first developed and it is not unusual today for multiple integrated circuit chips to be combined into a single laminated chip package. A continuing goal in the art is to provide integrated circuit packages which facilitate the nigh density mounting of integrated circuit devices. For example, the speed of operation of VHSIC and VLSI devices is often adversely effected by the length of interconnecting leads between respective integrated circuit devices. Thus, it is advantageous to package a plurality of devices in high density to provide the shortest possible interconnection lead configurations. Long lead lengths can produce unwanted inductance noise, capacitive loading effects, along with increased signal propagation times and signal skews. Thus, a primary consideration in developing improved high density electronic packaging is the length of the various leads interconnecting the integrated circuit components in the system. The invention described herein is directed to this consideration and significantly improves upon the state of the multichip packaging art.